Advancement in the wireless communications industry and the demand for high-data rate multi-media wireless connectivity has put stringent requirements on transceivers in terms of monolithic integration, power consumption, linearity, efficiency and noise. In some cases, these requirements are critical for a transmitter due to linearity, poor efficiency, and size of external components.
Heterodyne and direct conversion (homodyne) architectures have become widely adopted in wireless transmitter designs. To ensure reliable reception of a radio frequency (RF) signal, it may be necessary to down-convert the signal to baseband signals, filter out noise and interfering signals, and then demodulate the signal with a modem. Heterodyne designs have architectures that first down-convert a signal to intermediate frequency (IF) for efficient channel selection and then filter the signal to remove interfering signals, and amplify the signal for another step of down-conversion to the baseband frequency. Heterodyne transmitters have good I/Q matching (in-phase and quadrature signal matching), low local oscillation (LO) leakage, and high linearity, while wide range gain control can readily be implemented despite poor substrate isolation. However, off-chip surface acoustic wave (SAW) filters are required for both image rejection as well as to remove spurious harmonics at the output. Furthermore, the two sets of down-converters and respective LO synthesizers lead to a complex and area/power inefficient design. On the other hand, direct conversion transmitters do not require any image rejection filter, but such transmitters suffer from DC offset due to LO leakage and I/Q mismatch, thus degrading error vector magnitude (EVM).
Potentially, a modification of the heterodyne architecture allows a good tradeoff between the simplicity of homodyne systems and the performance of heterodyne systems. Such a modified architecture includes a first stage of up-conversion from baseband to IF performed digitally with quadrature local oscillators. By using FIF=Fs/4, the design of a digital quadrature modulator simplifies because the digital mixer's operation becomes either multiplying by 0 or bit sign flipping. Therefore, the digital mixer performs an inherently linear operation. After the first IF mixer, the in-phase and quadrature signals are added and a resulting signal (i.e., Nyquist rate or oversampled and noise shaped digital bitstream) is converted by a digital to analog converter (DAC). For very high speed digital to analog converters (update rates in the range of hundreds of MHz) targeted in digital-IF architectures, current steering DACs have become a desired option.
In a typical digital transmitter, a current steering DAC is followed by a transimpedance stage, a reconstruction filter, a variable gain amplifier (VGA) and an upconverting mixer. Each additional component degrades the linearity, I/Q matching, error vector magnitude (EVM), and spurious-free dynamic range (SFDR) of the transmitter output. It would thus be desirable to eliminate a number of additional components needed while still maintaining the necessary signal conversion within a transmitter.